An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon substrate. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. For other applications, such as oxide polishing, the filler layer is planarized until a predetermined thickness is left over the non planar surface. In addition, planarization is needed to planarize the substrate surface for photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier head. The exposed surface of the substrate is typically placed against a rotating polishing pad. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing liquid, such as a slurry with abrasive particles, is typically supplied to the surface of the polishing pad.
The carrier head provides a controllable load on the substrate to push it against the polishing pad. The carrier head has an inner ring which holds the substrate in place during polishing. The carrier head can also have an outer ring which surrounds the inner ring.